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utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? revision history revision description draft date preliminary rev. 0.5 original. mar, 2001 rev.1.0 1.separate industrial and commercial spec. 2.new waveforms. 3.add access time 55ns range. 4.the symbols ce1# and oe# and we# are revised as. 1 ce and oe and we . jul. 12,2001 rev.1.1 1.revised access time 55/70/100ns -rev 1.0: 55ns(max) for vcc=3.0v~3.6v 70/100 ns(max) for vcc=2.7v~3.6v 2.revised ?symbol? : 1 ce ce 3.revised absolute maximum ratings - v term : -0.3 to 4.6 -0.5 to 4.6v - p d : 1.0~1.5 1w - i out : 50 20ma 4.revised dc characteristics - v ih : 2.0 2.2v 5.revised ac characteristics - t oh & t blz : 5 10ns 6.revised 48-pin tfbga package outline dimension ?g -ball diameter : 0.3mm 0.35mm nov. 8. 2002 rev.1.2 1. revised standby current (ll-version) : 3ua(typ) 2ua(typ) 2. revised operating curr ent (iccmax) : 45/35/25ma 40/30/25ma 3. revised dc characteristics : a. operating power supply current (icc) 55ns (max) : 45 40ma 70ns (typ) : 25 20ma, 70ns (max) : 35 30ma 100ns (typ) : 20 16ma b. standby current(cmos) : ll-version (typ) : 3 2ua, 25 20ua dec 03,2002 rev.1.3 1. revised v oh (typ) : na 2.7v 2. add v ih (max)=v cc +2.0v for pulse width less than 10ns. v il (min)=v ss -2.0v for pulse width less than 10ns. 3. add order information for lead free product may 06.2003
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? features fast access time : 55/70/100 ns cmos low power operating operating current : 40/30/25 (icc max.) standby current : 20ua (typ.) l-version 2ua (typ.) ll-version single 2.7v~3.6v power supply operating temperature: commercial : 0 j ~70 j extended : -20 j ~80 j all ttl compatible inputs and outputs fully static operation three state outputs data retention voltage:1.5v (min.) data byte control : lb (i/o1~i/o8) ub (i/o9~i/o16) package : 48-pin 6mm 8mm tfbga general description the UT62L25716 is a 4,194,304-bit low power cmos static random access memory organized as 262,144 words by 16 bits. the UT62L25716 operates from a single 2.7v ~ 3.6v power supply and all inputs and outputs are fully ttl compatible. the UT62L25716 is designed for low power system applications. it is particularly well suited for use in high-density low power system applications. functional block diagram decoder i/o data circuit control circuit 256k x 16 memory array column i/o a0-a17 vcc vss i/o1-i/o8 lower byte i/o9-i/o16 upper byte ce2 oe we lb ub ce
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology in c. p80047 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? pin configuration lb a0 oe a1 ce2 a2 i/o9 a3 ub a4 i/o1 ce i/o10 a5 i/o11 a6 i/o3 i/o2 vss a17 i/o12 a7 vcc i/o4 vcc nc i/o13 a16 vss i/o5 i/o15 a14 i/o14 a15 i/o7 i/o6 i/o16 a12 nc a13 i/o8 we nc a9 a8 a10 nc a11 123456 h g c d e f a b tfbga pin description symbol description a0 - a17 address inputs i/o1 - i/o16 data inputs/outputs ce , ce2 chip enable input we write enable input oe output enable input lb lower-byte control ub upper-byte control v cc power supply v ss ground nc no connection truth table i/o operation mode ce ce2 oe we lb ub i/o1-i/o8 i/o9-i/o16 supply current standby h x x x l x x x x x x x x x h x x h high ? z high ? z high ? z high ? z high ? z high ? z i sb , i sb1 output disable l l h h h h h h l x x l high ? z high ? z high ? z high ? z i cc ,i cc1 ,i cc2 read l l l h h h l l l h h h l h l h l l d out high ? z d out high ? z d out d out i cc ,i cc1 ,i cc2 write l l l h h h x x x l l l l h l h l l d in high ? z d in high ? z d in d in i cc ,i cc1 ,i cc2 note: h = v ih , l=v il , x = don't care.
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 4.6 v commercial t a 0 to 70 j operating temperature extended t a -20 to 80 j storage temperature t stg -65 to 150 j power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 secs) tsolder 260 j *stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the dev ice or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. dc electrical characteristics (v cc = 2.7v~3.6v, t a = 0 j to 70 j / -20 j to 80 j (e)) parameter symbol test condition min. typ. max. unit power voltage v cc 2.7 3.0 3.6 v input high voltage v ih ? 1 2.2 - v cc +0.3 v input low voltage v il ? 2 -0.2 - 0.6 v input leakage current i li v ss ?? v in ?? v cc - 1 - 1 a output leakage current i lo v ss ?? v i/o ?? v cc; output disable - 1 - 1 a output high voltage v oh i oh = -1ma 2.2 2.7 - v output low voltage v ol i ol = 2.1ma - - 0.4 v 55 - 30 40 ma 70 - 20 30 ma operating power supply current i cc cycle time=min, 100%duty i/o=0ma, ce =v il 100 - 16 25 ma i cc1 tc y c l e = 1 s - 4 5 ma average operation current i cc2 100%duty,i i/o =0ma, ce ?? 0.2v, other pins at 0.2v or vcc-0.2v tc y c l e = 500ns - 8 10 ma standby current (ttl) i sb ce =v ih, other pins =v il or v ih - 0.3 0.5 ma -l - 20 80 a standby current (cmos) i sb1 ce =v cc -0.2v other pins at 0.2v or vcc-0.2v -ll - 2 20 a notes: 1. overshoot : vcc+2.0v for pulse width less than 10ns. 2. undershoot : vss-2.0v for pulse width less than 10ns. 3. overshoot and undershoot are sampled, not 100% tested.
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? capacitance (t a =25 j , f=1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v output load c l = 30pf, i oh /i ol = -1ma/2.1ma ac electrical characteristics (v cc =2.7v~3.6v, t a =0 j to 70 j / -20 j to 80 j (e)) (1) read cycle UT62L25716-55 UT62L25716-70 UT62L25716-100 parameter symbol min. max. min. max. min. max. unit read cycle time t rc 55 - 70 - 100 - ns address access time t aa - 55 - 70 - 100 ns chip enable access time t ace - 55 - 70 - 100 ns output enable access time t oe - 30 - 35 - 50 ns chip enable to output in low z t clz* 10 - 10 - 10 - ns output enable to output in low z t olz* 5 - 5 - 5 - ns chip disable to output in high z t chz* - 20 - 25 - 30 ns output disable to output in high z t ohz* - 20 - 25 - 30 ns output hold from address change t oh 10 - 10 - 10 - ns lb , ub access time t ba - 55 - 70 - 100 ns lb , ub to high-z output t bhz - 25 - 30 - 40 ns lb , ub to low-z output t blz 10 - 10 - 10 - ns (2) write cycle UT62L25716-55 UT62L25716-70 UT62L25716-100 parameter symbol min. max. min. max. min. max. unit write cycle time t wc 55 - 70 - 100 - ns address valid to end of write t aw 50 - 60 - 80 - ns chip enable to end of write t cw 50 - 60 - 80 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 45 - 55 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 25 - 30 - 40 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow* 5 - 5 - 5 - ns write to output in high z t whz* - 30 - 30 - 40 ns lb , ub valid to end of write t bw 45 - 60 - 80 - ns *these parameters are guaranteed by device char acterization, but not production tested.
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? timing waveforms read cycle 1 (address controlled) (1,2) t rc t aa data valid address dout t oh t oh previous data valid read cycle 2 ( ce and ce2 and oe controlled) (1,3,4,5) t rc t aa t ace t blz t oe t ohz t clz t bhz t oh t olz high-z data valid high-z t ba t chz address ce2 dout ce lb , ub oe notes : 1. we is high for read cycle. 2.device is continuously selected oe =low, ce =low , ce2=high, lb or ub =low . 3.address must be valid prior to or coincident with ce =low , ce2=high, lb or ub =low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz , t olz , t chz , t bhz and t ohz are specified with c l =5pf. transition is measured ? 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz .
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? write cycle 1 ( we controlled) (1,2,3,5,6) t wc t aw t cw t as t wp t bw t whz t ow t wr high-z (4) (4) address ce2 ce we lb , ub dout din data valid t dw t dh write cycle 2 ( ce and ce2 controlled) (1,2,5,6) t wc t aw t cw t as t wr t wp t bw t whz t dw t dh data valid high-z (4) address ce2 ce we lb , ub dout din
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? write cycle 3 ( lb , ub controlled) (1,2,5,6) t wc t aw t as t wr t cw t wp t bw t whz t dw t dh data valid address ce ce2 we lb , ub dout din high-z notes : 1. we , ce , lb , ub must be high or ce2 must be low during all address transitions. 2.a write occurs during the overlap of a low ce , high ce2, low we , lb or ub =low. 3.during a we controlled write cycle with oe low, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce , lb , ub low transition and ce2 high transition o ccurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured ? 500mv from steady state.
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? data retention characteristics (t a = 0 j to 70 j / -20 j to 80 j (e)) parameter symbol test condition min. typ. max. unit vcc for data retention v dr ce ? v cc -0.2v or ce2 ?? 0.2v 1.5 - 3.6 v data retention current i dr vcc=1.5v - l - 1 50 a ce ? v cc -0.2v or ce2 ?? 0.2v - ll - 0.5 20 a chip disable to data t cdr see data retention 0 - - ms retention time waveforms (below) recovery time t r 5 - - ms data retention waveform low vcc data retention waveform (1) ( ce controlled) v dr ? 1.5v ce ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr ce low vcc data retention waveform (2) (ce2 controlled) v dr ? 1.5v v cc(min.) v cc t r t cdr ce2 ?? 0.2v v il ce2 v cc(min.) v il low vcc data retention waveform (3) ( lb , ub controlled) v dr ? 1.5v lb,ub ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr lb,ub
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? package outline dimension 48 pin 6.0mmx8.0mm tfbga package outline dimension
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? ordering information commercial temperature part no. access time ( ns ) standby current ( a) typ. package UT62L25716bs-55l 55 20 48 pin bga UT62L25716bs-55ll 55 2 48 pin bga UT62L25716bs-70l 70 20 48 pin bga UT62L25716bs-70ll 70 2 48 pin bga UT62L25716bs-100l 100 20 48 pin bga UT62L25716bs-100ll 100 2 48 pin bga extended temperature part no. access time (ns) standby current ( a) typ. package UT62L25716bs-55le 55 20 48 pin bga UT62L25716bs-55lle 55 2 48 pin bga UT62L25716bs-70le 70 20 48 pin bga UT62L25716bs-70lle 70 2 48 pin bga UT62L25716bs-100le 100 20 48 pin bga UT62L25716bs-100lle 100 2 48 pin bga
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? ordering information (for lead free product) commercial temperature part no. access time ( ns ) standby current ( a) typ. package UT62L25716bsl-55l 55 20 48 pin bga UT62L25716bsl-55ll 55 2 48 pin bga UT62L25716bsl-70l 70 20 48 pin bga UT62L25716bsl-70ll 70 2 48 pin bga UT62L25716bsl-100l 100 20 48 pin bga UT62L25716bsl-100ll 100 2 48 pin bga extended temperature part no. access time (ns) standby current ( a) typ. package UT62L25716bsl-55le 55 20 48 pin bga UT62L25716bsl-55lle 55 2 48 pin bga UT62L25716bsl-70le 70 20 48 pin bga UT62L25716bsl-70lle 70 2 48 pin bga UT62L25716bsl-100le 100 20 48 pin bga UT62L25716bsl-100lle 100 2 48 pin bga
utron UT62L25716 rev. 1.3 256k x 16 bit low power cmos sram utron technology inc. p80047 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 13 ? this page is left blank intentionally.

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